1. Field of the Invention
The invention relates to the field of MOS integrated comparator circuits and more specifically to CMOS integrated comparator circuits.
2. Prior Art
In the design of complementary metal-oxide semiconductor (CMOS) integrated circuits, comparator circuits are used to detect small differences between the voltages of two input signals. A comparator circuit commonly includes a differential amplifier circuit for receiving two input voltages and generating an output current proportional to the voltage difference between the two inputs, coupled to an output circuit for converting the output current of the differential amplifier circuit to a suitable output voltage signal.
One application for an integrated comparator circuit is the decoding of digital information transmitted at high frequencies over transmission cables. Two rapidly changing voltage signals of varying amplitudes are decoded using a comparator circuit to compare the encoded digital information. For high data transmission frequencies with large amplitude voltage swings, prior art comparator circuits fail to decode the information correctly due to slow comparator response time to large input voltage swings. To allow reliable decoding of digital information transmitted at high frequencies, comparator circuits with faster response times to large input voltage swings are required. The overall response time of a comparator circuit is determined by the individual response times of the differential amplifier circuit and the output circuit.
Prior art differential amplifier circuits commonly include a current source coupled to a differential pair of transistors that are coupled to a current-mirror. Large voltage swings on the inputs to the differential pair of transistors increase the response time of prior art differential amplifier circuits considerably.
Prior art output circuits commonly include an inverter having a balance-point voltage. The balance-point voltage is the input voltage of the inverter that produces a substantially equal voltage at the output of the inverter. As commonly understood, the inverter output switches to a low state when the input voltage increases above the balance-point voltage and to a high state when the input voltage decreases below the balance-point voltage. If the input to the inverter is driven much higher than the balance-point voltage to switch the output to the low state or much lower than the balance-point voltage to switch the output to the high state, then the additional time needed to drive the inverter input below the balance-point voltage or above the balance-point voltage, respectively, in order to subsequently switch the output to the opposite state increases the response time of the inverter and, therefore, output circuit considerably.
The response time of the output circuit can be decreased by limiting the voltage swing at the inverter input. Some MOS read-only memory circuits prevent column lines from fully discharging in order to reduce the time to recharge the column lines as described in U.S. Pat. No. 4,223,394.
It is appreciated then that what is needed is a comparator circuit with a faster response time. Furthermore, the response time of the comparator circuit can be decreased by decreasing the response times of the differential amplifier circuit and the output circuit.